In order to make more efficient use of integrated circuit surface area, conventional two-dimensional semiconductor technology has evolved such that contemporary circuits are formed on multiple layers in a three-dimensional configuration. In such configurations, active devices and interconnects are formed in a layered relationship. During the formation of each subsequent layer, an inter-layer pathway, referred to in the art as a xe2x80x9cplugxe2x80x9d, or xe2x80x9cstudxe2x80x9d is electrically coupled between the various active devices and transmission lines of the different layers. To assist in aligning a plug, xe2x80x9clanding padsxe2x80x9d or xe2x80x9ctapsxe2x80x9d are formed in lower layers to serve as a target for the plugs passing from the upper layer. The landing pads are coupled to an underlying circuit or interconnect and are generally larger in surface area than the circuit or interconnect to serve as a wider-tolerance target for the plug.
Such multi-layered technology has enabled the design of highly-integrated memory devices, for example DRAM devices, having extremely high capacity, for example above 1 gigabyte. Such DRAM devices include multiple arrays of memory cells, densely and efficiently laid out under tight design constraints. Between the cell areas are peripheral regions, which include supporting circuitry and interconnect circuitry between the cells, as well as input/peripherals, and the like.
Any misalignmnent between the vertical plugs and the horizontal interconnect features can cause defects and reliability problems. To ensure that the plug aligns with a feature, the features are made larger than required, for example through the use of landing pads. The area by which the feature is made larger is referred to in the art as a xe2x80x9cborderxe2x80x9d around the vertical contact hole. Any excessive border area thus has a negative impact on circuit density.
Attempts have been made in the past to provide multiple layer interconnect, while reducing or eliminating the border area. These include circuits and fabrication procedures disclosed in U.S. Pat. Nos. 6,083,824, 5,612,254, and 4,966,870.
To a larger extent, the packing density of circuits is limited by how closely the interconnect metal between circuits can be formed without encroaching on each other. These limits are dictated by design rules that govern the separation of one level of contact from another, and by design rules for nesting tolerance or for borders used around contacts.
Other efforts have made toward reducing the high-aspect ratio of the holes made for inter-level interconnects, where the aspect ratio refers the height of a hole as compared to its width. In general, the deeper the hole, the more difficult it is to fabricate the hole. Using the line of an underlying circuit, for example a bit line of a DRAM memory device, as a landing pad, the aspect ratio of the interconnection hole can be significantly reduced.
A typical multiple-layer DRAM memory device includes a cell region and a peripheral region. The cell region includes active switching devices, coupled to vertically-oriented capacitors, that serve as data storage devices. A cell bit line serves as an interconnect to transfer data between peripheral circuit regions and the cell region. The peripheral region includes a number of bit lines, that function as local interconnects, or studs, electrically coupling between the various active devices and transmission lines of the different layers. An insulative oxide layer is formed above the bit lines, and an interconnect stud is opened through the oxide layer and connected to the bit line.
When the bit lines are used for local interconnection, for example especially in sense amplifier regions, the layers of circuits can become very dense and crowded. For example, to access the bit line from an upper layer, the region between the bit lines must be accurately etched to form a stud interconnect hole; both in a lateral direction, so as to avoid contact with adjacent bit lines, and in a vertical direction, so as to ensure that the hole is formed at the proper depth. Because the peripheral region, for example a sense amplifier region of a DRAM device, is often times densely populated with various interconnect paths, the cross-sectional area of any vertical stud interconnects should be minimized. Therefore, the above case requires subsequent formation of high-aspect-ratio studs that are difficult to achieve using contemporary fabrication processes.
Contemporary techniques of forming the interconnect stud are subject to several process limitations. These include horizontal misalignment, in a lateral direction, where the stud hole may be laterally misaligned with the underlying bit line during formation of the stud hole. Vertical misalignment can also occur, wherein the stud hole is not etched deep enough, so the stud does not make contact with the underlying bit line, or wherein the stud hole is etched too deeply, and is etched through the bit line.
To improve alignment accuracy, U.S. Pat. No. 5,895,239 discloses a technique for employing a bit line landing pad together with a bit line stud. However, this approach requires tight tolerances at either, or both, the top portions of the bit lines, including the landing pad, and bottom portions of the upper interconnect stud, so as to provide a minimal width at the top of the bit line, and a maximum width at the bottom of the upper interconnect stud. A wide stud top limits circuit density considerations, while a narrow stud bottom leads to increased contact resistance and an increased aspect ratio that is difficult to accurately fabricate. No provision is made for vertical alignment of the stud, so if the stud hole is slightly misaligned with the underlying bit line, a void can be formed in the underlying inter-layer dielectric adjacent the stud.
Another approach at multiple-layered interconnect is disclosed in U.S. Pat. No. 5,891,799. With reference to FIG. 1, in this approach, an etch-stop layer 206, for example a silicon nitride masking layer (Si3N4) is formed over an inter-layer dielectric (SiO2) 202, in turn formed over a metal layer 210 formed on a substrate 200. Stud holes 213A, 213B are patterned through the mask layer 206 and underlying dielectric layer 202 for the deposit of studs 212A, 212B to connect between the upper and lower layers. Once the studs 212A, 212B are formed, the masking layer 206 later serves as an etching reference for studs 214A, 214B formed through an upper masking layer 208 and upper dielectric layer 204. However, this technique suffers from a number of limitations. Since the Si3N4 masking layer 206, 208 is a high-stress-bearing material, and is formed indiscriminately as a layer over the entire circuit, this configuration imparts undue stress on the various layers, which may lead to warping of the circuit. Additionally, due to its high density, the masking layer prevents outgassing of impurities contained in the inter-layer dielectric, for example C, F, and Cl, during later high-temperature processes. The remaining Si3N4 masking layer would prevent the introduction of H2 and O2 during popular alloy processes, greatly affecting the conductive adhesiveness between the upper and lower metals.
Furthermore, this process is incompatible with contemporary memory fabrication processes, because the Si3N4 masking layer would be applied between bit lines. Dielectric spacers formed on each lateral side of a cell bit line prevent shorting between the cell bit line and the nearby capacitor. In order to make such spacers, it would be necessary to remove any masking layer between adjacent bit lines to allow for space for the capacitors to be inserted between the bit lines. However, this process would also remove any dielectric layer formed over the bit lines necessary for insulating the bit lines from the capacitors. This would also remove any masking layer on either side of the peripheral region bit lines, defeating the purpose of forming the masking layer in the first place.
The present invention is directed to a fabrication process and circuit that address the limitations of conventional techniques. For example, the present invention provides an etch-stop layer that is selectively patterned on only a portion of the underlying inter-layer dielectric, thereby allowing for outgassing during later fabrication processes. The remaining etch-stop layer is localized to only those portions surrounding the connecting media, for example surrounding the studs, between lower and upper contact holes. The surface area of the remaining etch-stop layer is preferably large enough so as to provide a suitable alignment target during formation of an overlying stud formed in an upper layer, yet small enough so as not to allow for sufficient outgassing, and so as to not interfere with neighboring contact holes, for example contact holes for nearby bit line landing pads.
In one aspect, the present invention is directed to a semiconductor device comprising a first dielectric layer formed on a substrate. A second dielectric layer is formed on the first dielectric layer. A stud is formed through the first and second dielectric layers, and a third dielectric layer is formed over a top of the stud. A first pad of first etch stop material is formed over the top surface of the stud and under the third dielectric layer.
The pad is preferably formed in a void region remaining after removal of a portion of the second dielectric layer. The third dielectric layer and the first etch stop material may comprise the same material.
The semiconductor device may further comprise a first circuit region formed in the first dielectric layer, the first circuit region including the stud; and a second circuit region formed in the first dielectric layer, the second circuit region including at least one conductive line and at least one spacer on a sidewall of the conductive line, the spacer being made of the same material as the first pad of the first etch stop material.
A second pad of a second etch stop material may be formed over the top surface of the stud and the first pad of the first etch stop material, the second pad of the second etch stop material being selectively patterned to cover only an area of the semiconductor device that includes the stud. The third dielectric layer, and the first and second etch stop materials may comprise the same material.
The semiconductor device may further include a first circuit region formed in the first dielectric layer, the first circuit region including the stud; and a second circuit region formed in the first dielectric layer, the second circuit region including at least one conductive line and at least one spacer on a sidewall of the conductive line, the spacer being made of the same material as the first pad of the first etch stop material, whereby the spacers and the first pad are formed simultaneously.
The third dielectric layer preferably has an etch selectivity with respect to the second dielectric layer, and may comprises etch stop material.
In another aspect, the present invention comprises a method of forming a semiconductor device. A first dielectric layer is formed on a substrate and a second dielectric layer is formed on the first dielectric layer. A stud is provided through the first and second dielectric layers, and a third dielectric layer is formed over the top of the stud and the second dielectric layer. A portion of the second dielectric layer is removed at the top of the stud, to create a void region in the second dielectric layer at the top of the stud and under the third dielectric layer. A first pad of a first etch stop material is provided in the void region.